Random Walk for Fast, Geometry-Agnostic IC Modelling

The sector of design tools for Integrated Circuits (ICs) is a critical link of the Semiconductor industry, with worldwide revenue of $9.3 billion in 2017 and annual growth rate appr. 9%. Helic’s tools are used to model and simulate Integrated Circuits under realistic operating conditions, to reduce the number prototyping cycles before production and to significant accelerate time-to-market. Recent developments in IC design, impose requirements for high density, integration of heterogeneous technologies, high operating frequencies and low power consumption, and have established electromagnetic Crosstalk noise as a major design constraint and a terrifying prospect for time-to-market delays, with huge potential consequences in lost revenues for the manufacturers. Recent developments in IC design, impose requirements for high density, integration of heterogeneous technologies, high operating frequencies and low power consumption, and have established electromagnetic Crosstalk noise as a major design constraint and a terrifying prospect for time-to-market delays, with huge potential consequences in lost revenues for the manufacturers. Practically, a new segment has been emerging in the EDA market, to cover new needs for the detection and avoidance of electromagnetic Crosstalk noise, in the high value and fast-growing markets of high-performance Digital ICs (e.g. GPU, CPU), memories and heterogeneous Systems in Package (SiP).

The proposed method for calculating parasitic capacitances is based on an innovative application of the Random Walk method and aims to solve the electrostatic problem of fast parasitic capacitances extraction, also in a manner extensible to future application in 3D ICs. The following performance targets will be met:

• Accuracy equal or better to that of existing tools (max error 5%-10%)
• Reduced execution time due to intrinsically parallelisable nature
• Small memory footprint

The main proposed research axes are:

1. Development of a Random Walk algorithm for parasitic capacitances extraction
2. Development of Computation Geometry methods that will support the proposed Random Walk method, with particular emphasis in the efficient solution of the Maximum Empty Cube problem
3. Optimisation of Helic’s modelling engine via pre-characterisation of Green functions used for sampling

The new modelling engine will be integrated into Helic’s existing workflow and will be used experimentally to extract parasitic models of verification structures and IC blocks that will be designed during the Project. For the algorithms’ development, Helic will collaborate with the ATHENA Research Centre team that has internationally unique experience in geometric and scientific calculations. Helic will also collaborate with Prof. E. Papadopoulou (U. Svizzera Italiana, ex IBM) who has strong experience in the industrial implementation of geometric calculations applied to Microelectronics problems. The University of Patras will guide overall development as an expert end-user of IC design tools and will deliver designs and measurements of verification structures and IC blocks in modern technology nodes (28nm or 40nm).